1. Field of the Invention
This invention relates to stacked wafer integrated circuits, and more particularly to use of a barrier layer on patterned connecting structures to prevent diffusion and electromigration.
2. Background of the Invention
Stacked integrated circuits have conductors extending between bonded wafers. These conductors can have exposed surfaces which can lead to reliability problems. FIG. 1 is a side cross section view of an example conventional stacked integrated circuit 100 that illustrates such problems. The stacked integrated circuit 100 has a first device structure 102. The first device structure 102 includes a substrate layer 104 and an oxide layer 106. Copper conductors 108 extend from the oxide layer 106 of the first device structure 102 to a second device structure 110. The conductors 108 have exposed surfaces 112 because the first and second device structures 102, 110 are spaced a distance 114 apart. Because the conductors 108 have exposed surfaces 112, and because copper can diffuse through oxide easily, issues such as copper diffusion and electromigration may occur. This can lead to shorting of the stacked integrated circuit 100 or voids in the conductors 108. Either of these problems can cause the stacked integrated circuit 100 to malfunction.